1. Field of the Invention
The present invention relates to a replica network for linearizing switched capacitor circuits.
2. Background Art
Switched capacitor sampling networks are commonly used in signal processing applications. They can be efficiently implemented using CMOS technology and are easily integrated with other networks. Among other functions, switched capacitor sampling networks are used for filtering, sample and hold, analog-to-digital conversion, and digital-to-analog conversion.
High performance switch capacitor sampling networks are typically configured as differential circuits. As compared with single-ended designs, a differential embodiment enjoys improved power supply noise rejection, double the output range, and cancellation of even-order distortion components.
FIG. 1A is a schematic diagram of a typical differential switched capacitor sampling network 100. In FIG. 1A, network 100 comprises eight switches: S1 102, S2 104, S3 106, S4 108, S5 110, S6 112, S7 114, and S8 116. Collectively, S1 102, S2 104, S3 106, and S4 108 are referred to as signal conducting switches, while S5 110, S6 112, S7 114, and S8 116 are collectively referred to as summing junction switches.
FIG. 1B illustrates a two-phase nonoverlapping clock scheme 118 defined by four clock waveforms: xcfx861 120, xcfx861D 122, xcfx862 124 and xcfx862D 126. The position of each switch at any given time is determined by its corresponding clock waveform. In a representative embodiment, a switch is open when its corresponding clock waveform is xe2x80x9coffxe2x80x9d and closed when its corresponding clock waveform is xe2x80x9con.xe2x80x9d One skilled in the art would recognize that network 100 could be configured with other relationships between the state of the switches and their corresponding clock waveforms.
Clock scheme 118 is configured so that xcfx861 120 and xcfx861D 122 are on when xcfx862 124 and xcfx862D 126 are off. Clock waveforms xcfx861D 122 and xcfx862D 126 are similar to, respectively, clock waveforms xcfx861 120 and xcfx862 124. However, the falling edges of xcfx861D 122 and xcfx862D 126 are not initiated until after xcfx861 120 and xcfx862 124 have returned to their xe2x80x9coffxe2x80x9d states. Together, clock waveforms xcfx861 120 and xcfx861D 122 define a sampling phase of clock scheme 118 while clock waveforms xcfx862 124 and xcfx862D 126 define a transferring phase.
Network 100 further comprises a positive voltage sampling capacitor C1+128, a negative voltage sampling capacitor C1xe2x88x92 130, and a differential integrator 132. Differential integrator 132 comprises an operational amplifier 134 with an inverting terminal Txe2x88x92 136, a noninverting terminal T+ 138, a positive voltage output signal Vo+ 140, and a negative voltage output signal Voxe2x88x92 142. A positive voltage feedback capacitor C2+ 144 is connected in parallel with operational amplifier 134 between Txe2x88x92 136 and Vo+ 140. A negative voltage feedback capacitor C2xe2x88x92 146 is connected in parallel with operational amplifier 134 between T+ 138 and Voxe2x88x92 142. Both a positive voltage input signal Vi+ 146 and a negative voltage input signal Vixe2x88x92 148 are received by network 100.
Switch S1 102 is disposed between Vi+ 146 and C1+ 128. Switch S2 104 is disposed between Vixe2x88x92 148 and C1+ 128, such that S1 102 and S2 104 are connected in parallel with each other at a node N1 150 upstream of C1+ 128. Switch S3 106 is disposed between Vi+ 146 and C1xe2x88x92 130. Switch S4 108 is disposed between Vixe2x88x92 148 and C1xe2x88x92 130, such that S3 106 and S4 108 are connected in parallel with each other at a node N2 152 upstream of C1xe2x88x92 130.
Switch S5 110 is disposed between a node N3 154 downstream of C1+ 128 and Txe2x88x92 136. Switch S6 112 is disposed between N3 154 and an analog ground connection 156. Switch S7 114 is disposed between a node N4 158 downstream of C1xe2x88x92 130 and T+ 138. Switch S8 116 is disposed between N4 158 and analog ground connection 156.
Operation of network 100 can be explained by tracing the circuits that are established in response to the cycling of the clock waveforms of clock scheme 118.
At a time t0, clock waveforms xcfx861 120 and xcfx861D 122 cycle to the on state while clock waveforms xcfx862 124 and xcfx862D 126 remain in the off state. In response to the on state of xcfx861 120, switches S6 112 and S8 116 close. In response to the on state of xcfx861D 122, switches S1 102 and S4 108 close. With S1 102 and S6 112 closed, a circuit is established between Vi+ 146 and analog ground 156 through C1+ 128. This circuit allows Vi+ 146 to be sampled as a charge on an upstream plate P1u+ 160 of C1+ 128. The value of this charge is equal to the product of the capacitance of C1+ 128 and the voltage of Vi+ 146. Likewise, with S4 108 and S8 116 closed, a circuit is established between Vi+ 148 and analog ground 156 through C1xe2x88x92 130. This circuit allows Vixe2x88x92 148 to be sampled as a charge on an upstream plate P1uxe2x88x92 162 of C1+ 130. The value of this charge is equal to the product of the capacitance of C1xe2x88x92 130 and the voltage of V1xe2x88x92 148.
At a time t1, clock waveform xcfx861 120 cycles to the off state, while xcfx861D 122 remains in the on state. Clock waveforms xcfx862 124 and xcfx862D 126 remain in the off state. In response to the off state of xcfx861 120, switches S6 112 and S8 116 open. Opening switch S6 112 breaks the circuit between V1+ 146 and analog ground 156. This isolates the charge stored on upstream plate P1u+ 160, thus effectively sampling Vi+ 146. Likewise, opening switch S8 116 breaks the circuit between Vixe2x88x92148 and analog ground 156. This isolates the charge stored on upstream plate P1uxe2x88x92162, thus effectively sampling Vixe2x88x92 148.
At a time t2, clock waveform xcfx861D 122 cycles to the off state. Clock waveforms xcfx861 120, xcfx862 124, and xcfx862D 126 remain in the off state. In response to the off state of xcfx861D 122, switches S1 102 and S4 108 open. By delaying the opening of switches S1 102 and S4 108 until after switches S6 112 and S8 116 have been opened, and thus isolating the charges stored on C1+ 128 and C1xe2x88x92 130, the sampled signals are unaffected by the charge injection that occur after switches S6 112 and S8 116 have been opened. Particularly, the sampled signals are not distorted by any charge injection resulting from the opening of switches S1 102 and S4 108.
At a time t3, clock waveforms xcfx862 124 and xcfx862D 126 cycle to the on state while clock waveforms xcfx861 120 and xcfx861D 122 remain in the off state. In response to the on state of xcfx862 124, switches S5 110 and S7 114 close. In response to the on state of xcfx862D 126, switches S2 104 and S3 106 close. With S2 104 and S5 110 closed, a circuit is established between Vixe2x88x92 148 and differential integrator 132 through C1+ 128. This circuit enables the charge on upstream plate P1u+ 160 to be transferred to differential integrator 132. One skilled in the art would recognize that the transferred charge is defined by Eq. (1):
Q=Csxc3x97[Vi+xe2x88x92Vixe2x88x92],xe2x80x83xe2x80x83Eq. (1) 
where Cs equals the value of the capacitance of C1+ 128. As it is desired that the charge transferred to differential integrator 132 equals the charge stored on capacitor C1+ 128, the use of a differential circuit enables C1+ 128 to have a smaller value of capacitance than it would have in a single-ended switched capacitor integrator configuration having the same gain and the same value of capacitance for the feedback capacitor. Advantageously, a smaller value for C1+128: (1) increases the speed of network 100, (2) reduces the degradation in bandwidth of frequencies that network 100 can support, and (3) enables the feedback factor of differential integrator 132 to be nearer to unity, where feedback factor is defined by Eq. (2):
Feedback Factor=Cf/[Cf+Cs].xe2x80x83xe2x80x83Eq. (2) 
Likewise, with S3 106 and S7 114 closed, a circuit is established between Vi+ 146 and differential integrator 132 through C1xe2x88x92 130. This circuit enables the charge on upstream plate P1uxe2x88x92 162 to be transferred to differential integrator 132 in the same manner as described above.
At a time t4, clock waveform xcfx862 124 cycles to the off state, while xcfx862D 126 remains in the on state. Clock waveforms xcfx861 120 and xcfx862 122 remain in the off state. In response to the off state of xcfx862 124, switches S5 110 and S7 114 open. Opening switch S5 110 breaks the circuit between Vixe2x88x92 148 and differential integrator 132. This isolates the charge transferred to differential integrator 132 from C1+ 128. Likewise, opening switch S7 114 breaks the circuit between Vi+146 and differential integrator 132. This isolates the charge transferred to differential integrator 132 from C1xe2x88x92 130.
At a time t5, clock waveform xcfx862D 126 cycles to the off state. Clock waveforms xcfx861 120, xcfx862 122, and xcfx862 124 remain in the off state. In response to the off state of xcfx862D 126, switches S2 104 and S3 106 open. By delaying the opening of switches S2 104 and S3 106 until after switches S5 110 and S7 114 have been opened, the transferred signals are unaffected by the charge injection that occur after switches S5 110 and S7 114 have been opened. Particularly, the transferred signals are not distorted by any charge injection resulting from the opening of switches S2 104 and S3 106.
At a time t6, clock waveforms xcfx861 120 and xcfx861D 122 cycle to the on state while clock waveforms xcfx862 124 and xcfx862D 126 remain in the off state. The response of network 100 to the on state of xcfx861 120 and xcfx861D 122 is identical to the response to the on state at time t0 as explained above. Likewise, at times subsequent to t6, network 100 operates in the manner explained above.
In a more typical embodiment, the switches of FIG. 1A are implemented with MOSFETs. FIG. 2 is a schematic diagram of a differential switched capacitor sampling network 200, with MOSFET switches. This circuit is described in Stephen R. Norsworthy et al., Delta-Sigma Data Converters: Theory, Design, and Simulation, The Institute of Electrical and Electronics Engineers, Inc. 1997, which is incorporated herein by reference.
In FIG. 2, signal conducting switches S1 202, S2 204, S3 206, and S4 208 are implemented with CMOSFETs, while summing junction switches S5 210, S6 212, S7 214, and S8 216 are implemented with NMOSFETs. However, one skilled in the art would recognize that the type of MOSFETs used to implement the switches would be a function of, among other considerations, the signal environment in which network 200 would operate. The use of CMOSFETs for the signal conducting switches extends the range of voltages over which the signal conducting switches would conduct. The use of CMOSFETs for this particular purpose is well understood in the art.
For each MOSFET switch of FIG. 2, the signal path is between its source and drain terminals. The state of the MOSFET switch is controlled by a clock waveform applied to its gate terminal. For the PMOSFET portion of a CMOSFET, the clock waveform is opposite of the clock waveform used for the NMOSFET portion. Thus, a clock waveform xcfx861D [bar] 218 is in the on state when clock waveform xcfx861D 122 is in the off state and vice versa. Likewise, a clock waveform xcfx862D [bar] 220 is in the on state when clock waveform xcfx862D 126 is in the off state and vice versa.
While delaying the opening of the signal conducting switches until after the summing junction switches have been opened isolates the sampled signal from distortions due to charge injections from the signal conducting switches, this clock scheme does not protect the sampled signal from distortions due to: (1) variations in the resistances of the signal conducting switches that operate in an environment of a varying voltage signal, or (2) charge injections from the summing junction switches.
Where a switch in a differential switched capacitor sampling network is implemented as a MOSFET, the resistance of the switch is defined by Eq. (3):
R=1/[kxc3x97(VGSxe2x88x92VTxe2x88x92VDS)],xe2x80x83xe2x80x83Eq. (3) 
where k is a constant, VGS is the voltage potential between the gate and source terminals, VT is the threshold voltage, and VDS is the voltage potential between the drain and source terminals of the MOSFET. These parameters are well understood in the art.
Applying Eq. (3) to a signal conducting MOSFET switch of FIG. 2, the skilled artisan will appreciate that when the signal conducting MOSFET switch (e.g., S1 202, S2 204, S3 206, or S4 208) is on, a signal with a varying voltage is applied to the source terminal, while a constant voltage (i.e., the clock) is applied to the gate terminal. This produces a voltage VGS that varies in a signal dependent manner. This, in turn, results in the MOSFET switch having a resistance R whose value is signal dependent. As resistance R of the MOSFET switch varies, the drop in the voltage potential of the signal across the switch also changes. Changes in this drop in voltage distort the voltage potential of the signal that is sampled by a sampling capacitor. The distortion is signal dependent. This phenomenon is referred to as track mode distortion.
Meanwhile, delaying the opening of a signal conducting switch during the transferring phase (e.g., S2 204 or S3 206) until after its corresponding summing junction switch connected to the differential integrator (e.g., S5 210 or S7 214) has been opened exposes the transferred signal to distortions from charge injections from the summing junction switch connected to the differential integrator. Specifically, as the summing junction switch connected to the differential integrator is opened, a residual charge retained on it will have two paths through which to dissipate: (1) from the summing junction switch, through the sampling capacitor and the signal conducting switch, and towards the signal, and (2) from the summing junction switch towards the differential integrator.
The total residual charge will divide between these two paths according to the resistance that each path presents. From FIGS. 1A, 1B, and 2, it can be observed that at t4 the signal conducting MOSFET switch (e.g., S2 202 or S3 206) is closed while the summing junction MOSFET switch (e.g., S5 210 or S7 214) is being opened. As explained above, the resistance R of the closed signal conducting MOSFET switch is signal dependent. Therefore, the amount of the total residual charge that dissipates through the closed signal conducting MOSFET switch will also be signal dependent. Because the amount of the total residual charge that dissipates towards the differential integrator is the difference between the total residual charge and the amount of the total residual charge that dissipates through the closed signal conducting MOSFET switch, the amount of the total residual charge that dissipates towards the differential integrator will also be signal dependent and distort the signal transferred to the differential integrator.
Previous efforts to correct for signal dependent distortion in differential switched capacitor sampling networks have used midrange threshold voltage (about 0.3 volts) MOSFET switches. Differential switched capacitor sampling networks using these devices have been shown to reduce distortion. However, fabrication of these MOSFET switches requires the use of expensive extra mask layers. Also, at larger voltage input signal amplitudes and at higher voltage input signal frequencies, this approach has been shown to be ineffective at reducing signal distortion.
Alternatively, bootstrap capacitors have been used to buffer against changes in voltage between the gate and source terminals of signal conducting MOSFET switches. FIG. 3 is a schematic diagram of a signal conducting MOSFET switch 300 with a bootstrap capacitor 302 connected between a gate terminal 304 and a source terminal 306. During the on state of the clock waveform, bootstrap capacitor 302 acts to maintain VGS at a relatively constant voltage. As can be seen by applying Eq. (3), this mitigates the variation in the resistance R of signal conducting MOSFET switch 300 and thus reduces the degree of signal dependent distortion. During the off state of the clock waveform, bootstrap capacitor 302 is connected between a voltage source 308 and ground 310. This is done so that bootstrap capacitor 302 can be charged by voltage source 308 to enable it to perform its function during the on state of the clock waveform.
While the use of bootstrap capacitors has proven to be an adequate solution in many applications, it does present several disadvantages. Specifically, the bootstrap capacitors must be relatively large (on an order of magnitude that is four to five times the capacitance between the gate and source terminals of the signal conducting MOSFET switches) and they consume a relatively large amount of power. Furthermore, of the three parameters that determine the resistance R of the signal conducting MOSFET switchesxe2x80x94VGS, VT, and VDSxe2x80x94the use of bootstrap capacitors essentially addresses only one of these factors: VGS. This limits the accuracy of this solution for use in high precision applications. What is needed is a mechanism that controls the resistance R of a signal conducting MOSFET switch so that the resistance R is independent of the signal voltage and the switched capacitor circuit is linearized.
The present invention relates to a replica network for linearizing switched capacitor circuits. A bridge circuit with a MOSFET resistor disposed in a resistor branch of the bridge circuit is provided. A noninverting terminal of an operational amplifier is connected to a first node of the bridge circuit and an inverting terminal of the operational amplifier is connected to a second node of the bridge circuit. The second node is separated from the first node by a third node of the bridge circuit. An output of the operational amplifier is provided to a gate terminal of the MOSFET resistor and to the gate terminal of the MOSFET switch, thereby controlling the voltage to the gate terminal of the MOSFET switch.
In an embodiment, a compensation capacitor is connected in parallel between the output and the second node. In another embodiment, an analog ground is connected to a third node of the bridge circuit. In yet another embodiment, a voltage input signal is connected to a fourth node of the bridge circuit.
Preferably, the resistance of a first resistor connected between the first node and the third node equals the resistance of a second resistor connected between the second node and the third node. Preferably, the MOSFET resistor is connected between the second node and the fourth node. Preferably, the resistance of a third resistor connected between the first node and the fourth node is smaller than the resistance of the first resistor or the second resistor.
In an embodiment, the output of the operational amplifier controls the resistance of the MOSFET resistor so that the resistance of the MOSFET resistor equals the resistance of the third resistor. In another embodiment, the output of the operational amplifier controls the resistance of the MOSFET switch so that the resistance of the MOSFET switch equals the resistance of the third resistor. Preferably, the MOSFET resistor is similar to (i.e., the same type and/or size) the MOSFET switch. Preferably, the MOSFET resistor has a threshold voltage less than or equal to zero volts. Advantageously, MOSFETs with threshold voltages at this level are inexpensive to fabricate. In an embodiment, the MOSFET resistor is a native NMOSFET device.
In an embodiment, a first switch is disposed within the connection between the output and the gate terminal of the MOSFET switch. In a related embodiment, the first switch cycles to an open state and a closed state in response to an on state and an off state of a first clock waveform. In another related embodiment, a second switch is connected between a fifth node and analog ground. The fifth node is disposed within the connection between the first switch and the gate terminal of the MOSFET switch. In yet another related embodiment, the second switch cycles to an open state and a closed state in response to an on state and an off state of a second clock waveform.
In an emodiment, the replica network comprises two replica networks. In a related embodiment, each replica network receives a voltage input signal from a differential circuit. In another related embodiment, the differential circuit is a differential switched capacitor sampling network.
Unlike the use of a bootstrap capacitor, which acts to maintain VGS of a MOSFET switch at a relatively constant voltage and thus mitigates the variation in the resistance of the MOSFET switch, the replica network of the present invention acts to vary VGS as necessary to peg the resistances R of the MOSFET switch to the fixed resistance value of resistor in the bridge circuit.
In this manner, the replica network of the present invention provides a mechanism that controls the resistance of the MOSFET switch so that it is independent of the signal voltage. For a differential switched capacitor sampling network, this mitigates signal dependent distortion due to charge injection from the summing junction switches during the transferring phase and eliminates track mode distortion due to variations in the resistances of the signal conducting MOSFET switches during the sampling phase. Thus, the replica network of the present invention linearizes the switched capacitor circuit.